DYNAMIC CIRCUITRY USING PULSE AMPLIFICATION TO REDUCE METASTABILITY

摘要

Synchronisation circuitry 2 comprises a first dynamic circuit stage 4 generating a first stage state signal which is pulse amplified by pulse amplifying circuitry 8 to generate a pulse amplified signal. The pulse amplified signal is supplied to a second dynamic circuit stage 6 where it is used to control generation of a second stage state signal. The pulse amplifying circuitry 8 comprises a chain of serially connected skewed inverters 20, 22. The action of the pulse amplifying circuitry 8 is to reduce the probability of metastability in the output of the second dynamic stage 6.

主权项

1. Circuitry for receiving an input signal having an input signal value and for generating an output signal having an output signal value dependent upon said input signal value, said buffer circuit comprising:
a first circuit stage configured to receive said input signal and to generate a first stage state signal in dependence upon said input signal; pulse amplifying circuitry configured to receive and to pulse amplify said first stage state signal to generate a pulse amplified signal having a pulse amplified signal value such that a pulse in said first stage state signal, during which said first stage state signal changes from a first state signal value toward a second state signal value and then returns to said first state signal value, is amplified; a second circuit stage comprising:
second stage reset circuitry configured to reset a second stage state signal to a second stage reset signal value during a second stage reset period;output capture circuitry configured to receive said pulse amplified signal during a second stage evaluation period and:
(i) if said pulse amplified signal value has a first value, then to leave said second stage state signal at said second stage reset signal value; and(ii) if said pulse amplified signal value has a second value, then to change said second stage state signal from said second stage reset signal value to a second stage set signal value; and output generating circuitry configured to generate said output signal in dependence upon said second stage state signal.