发明名称 |
THICK CONDUCTIVE STACK PLATING PROCESS WITH FINE CRITICAL DIMENSION FEATURE SIZE FOR COMPACT PASSIVE ON GLASS TECHNOLOGY |
摘要 |
An integrated circuit device includes a substrate, and a first interlayer dielectric layer on the substrate that includes a first conductive layer and a second conductive layer. The integrated circuit device also includes a first conductive stack including a third conductive layer coupled to a portion of the second conductive layer with a first via. The integrated circuit device further includes a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate. The integrated circuit device also includes a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer. |
申请公布号 |
US2015014812(A1) |
申请公布日期 |
2015.01.15 |
申请号 |
US201414149530 |
申请日期 |
2014.01.07 |
申请人 |
QUALCOMM Incorporated |
发明人 |
LAN Je-Hsiung;ZUO Chengjie;YUN Changhan Hobie;KIM Jonghae;KIM Daeik Daniel;VELEZ Mario Francisco;MIKULKA Robert Paul;MUDAKATTE Niranjan Sunil |
分类号 |
H01L49/02 |
主分类号 |
H01L49/02 |
代理机构 |
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代理人 |
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主权项 |
1. An integrated circuit device, comprising:
a substrate; a first interlayer dielectric layer on the substrate comprising a first conductive layer and a second conductive layer; a first conductive stack comprising a third conductive layer coupled to a portion of the second conductive layer with a first via; a second conductive stack comprising a fourth conductive layer directly on a portion of the third conductive layer that is isolated from the substrate; and a second interlayer dielectric layer surrounding the third conductive layer and the fourth conductive layer. |
地址 |
San Diego CA US |