发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 An MV-PMOS and MV-NMOS configuring a high side drive circuit are formed in an n-type isolation region formed on a p-type semiconductor substrate. The MV-NMOS is connected to a p-type isolation region of an intermediate potential in the interior of the n-type isolation region. An n-type epitaxial region is provided in a surface layer of the p-type semiconductor substrate on the outer side of the n-type isolation region, and a p-type GND region of a ground potential (GND) is provided on the outer side of the n-type epitaxial region. A cavity is provided between the p-type semiconductor substrate and n-type epitaxial region between the high side drive circuit and p-type GND region, and a p-type diffusion region is provided penetrating the n-type epitaxial region and reaching the cavity. The intermediate potential is applied to the p-type isolation region.
申请公布号 US2015014783(A1) 申请公布日期 2015.01.15
申请号 US201414499707 申请日期 2014.09.29
申请人 FUJI ELECTRIC CO., LTD. 发明人 IMAI Tomohiro;YAMAJI Masaharu
分类号 H01L27/092;H01L29/10;H01L29/06 主分类号 H01L27/092
代理机构 代理人
主权项 1. A semiconductor integrated circuit device, comprising: a second conductivity type region, provided in a surface layer of a first conductivity type semiconductor substrate, in which a circuit portion is formed and to which is applied a first potential, which is a high voltage potential of a power supply of the circuit portion; a first conductivity type well region, provided in the interior of the second conductivity type region and configuring the circuit portion, to which is applied a second potential, which is a low voltage potential of the power supply; a first conductivity type low potential region, provided in a surface layer of the first conductivity type semiconductor substrate on the outer side of the second conductivity type region, to which is applied a third potential lower than the second potential; a cavity selectively provided between the circuit portion and first conductivity type low potential region and between the first conductivity type semiconductor substrate and second conductivity type region; and a first conductivity type region penetrating the second conductivity type region and reaching the cavity.
地址 Kawasaki-shi JP