发明名称 INTEGRATED CIRCUIT AND TEST STRUCTURE
摘要 <p>PROBLEM TO BE SOLVED: To judge resistance of a via, by a method wherein, in a position alignment between a path of a metallization layer and the corresponding via, or between the via and the corresponding path, a contact area between the path and the via is corrected with respect to a normal contact area. SOLUTION: First and second path parts 21, 22 are extended to a direction for corresponding vias 24, 25 and come close to all path parts neighboring the via on the same metallization layer from a common side. A continuous part 23 is not placed so that it comes nearer to one of the vias 24, 25 with substantially larger than a width of the via. A contact area is equal irrespective of a direction and an orientation of offsets between a path 20 and the vias 24, 25. All resistances in a part of the predetermined number of vias and paths are calculated, and a value of one via resistance can be obtained, and it is possible to uniformize more the respective via resistances in the entire integrated circuit and to judge an individual via resistance.</p>
申请公布号 JPH11251315(A) 申请公布日期 1999.09.17
申请号 JP19980369115 申请日期 1998.12.25
申请人 ST MICROELECTRONICS SA 发明人 GAYET PHILIPPE;BRUNEL CHANTAL;MARTIN STEPHANE
分类号 H01L21/3205;G01R31/28;G03F7/20;H01L23/52;H01L23/528;(IPC1-7):H01L21/320 主分类号 H01L21/3205
代理机构 代理人
主权项
地址