发明名称 PRIOD SIGNAL GENERATION CIRCUIT
摘要 <p>A period signal generation circuit includes a first buffer unit suitable for buffering a buffer signal and output an output signal; and a second buffer unit suitable for buffering the output signal and output a period signal, wherein each of the first and second buffer units includes a resistor element coupled between a body of a metal oxide semiconductor (MOS) transistor and a source.</p>
申请公布号 KR20150005365(A) 申请公布日期 2015.01.14
申请号 KR20130079241 申请日期 2013.07.05
申请人 SK HYNIX INC. 发明人 KANG, MAN KEUN
分类号 H03K19/0185 主分类号 H03K19/0185
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