Structure, method and system for complementary strain fill for integrated circuit chips

摘要

A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.

主权项

1. A structure, comprising:
a first region of an integrated circuit having an unequal number of p-channel and re-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of said first region, said first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of said first region, said second stressed layer of a second stress type, said second stress type opposite from said first stress type; and a second region of said integrated circuit, said second region not containing FETs, said second region containing first sub-regions of said first stressed layer surrounded by second sub-regions of said second stressed layer or said second region containing first sub-regions of said second stressed layer surrounded by second sub-regions of said first stressed layer.