Negative voltage generator and semiconductor memory device

摘要

A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

主权项

1. A negative voltage generator, comprising:
a negative voltage generating unit including a first coupling capacitor and a second coupling capacitor, and configured to select at least one of the first and second coupling capacitors corresponding to a parasitic capacitance of a bit line to be charged by the selected coupling capacitors, and to charge the at least one selected coupling capacitor to a negative voltage; and a switching unit configured to select the bitline to be charged in response to the data, and to connect the at least one charged coupling capacitor to the selected bitline, wherein the first coupling capacitor has a first electrode and a second electrode connected to an output node of the negative voltage generating unit, and the second coupling capacitor has a third electrode and a fourth electrode connected to the output node, and wherein negative voltage generating unit comprises:
an inverter configured to invert a write assist signal;a first switch configured to switchably connect the output terminal of the inverter to the first electrode of the first coupling capacitor in response to a first bank select signal;an OR-gate configured to perform an OR operation on the first bank select signal and a second bank select signal;a second switch configured to selectively connect the output terminal of the inverter to the third electrode of the second coupling capacitor in response to an output signal of the OR-gate; anda pull-down transistor configured to pull down the voltage of the output node in response to an inverted write assist signal.