发明名称 Integrated circuits and methods for fabricating integrated circuits with capping layers between metal contacts and interconnects
摘要 Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes forming a metal contact structure that is electrically connected to a device. A capping layer is selectively formed on the metal contact structure, and an interlayer dielectric material is deposited over the capping layer. A metal hard mask is deposited and patterned over the interlayer dielectric material to define an exposed region of the interlayer dielectric material. The method etches the exposed region of the interlayer dielectric material to expose at least a portion of the capping layer. The method includes removing the metal hard mask with an etchant while the capping layer physically separates the metal contact structure from the etchant. A metal is deposited to form a conductive via electrically connected to the metal contact structure through the capping layer.
申请公布号 US8932911(B2) 申请公布日期 2015.01.13
申请号 US201313778558 申请日期 2013.02.27
申请人 GLOBALFOUNDRIES, Inc. 发明人 Huisinga Torsten;Peters Carsten;Ott Andreas;Preusse Axel
分类号 H01L21/4763;H01L21/82;H01L21/311;H01L21/44;H01L23/48;H01L23/52;H01L29/40;H01L21/02;H01L21/768 主分类号 H01L21/4763
代理机构 Ingrassia Fisher & Lorenz, P.C. 代理人 Ingrassia Fisher & Lorenz, P.C.
主权项 1. A method for fabricating integrated circuits, the method comprising: forming a metal structure including a first metal over a semiconductor substrate; selectively depositing a capping layer on the metal structure; forming a metal pattern over the capping layer, wherein the first metal and the metal pattern comprise the same metal, TiN (Titanium Nitride); forming an aperture to the capping layer using the metal pattern as a mask; and removing the metal pattern with an etchant.
地址 Grand Cayman KY