Semiconductor chip package including voltage generation circuit with reduced power noise

摘要

A semiconductor chip package eliminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit, and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and a mounting substrate to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package.

主权项

1. A semiconductor chip package comprising:
an integrated circuit chip including a voltage generation circuit that receives an external voltage to generate a supply voltage greater than the external voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit; and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package.