Multiple delay locked loop integration system and method

摘要

A delay locked loop (DLL) circuit having an expanded operating frequency range is achieved by providing multiple DLLs, each having a different range of operating frequencies. A selection mechanism selects the DLL with the appropriate operating frequency range. The output of the selected DLL is used as the output of the delay locked loop circuit and is fed back to the input of the selected DLL so as to achieve phase lock with an input signal. The selection mechanism can operate in accordance with, among other things, a metallization mask option, the state of one or more pins, the state of one or more bits of a software accessible register or storage device, or the output of a frequency detector which detects the frequency of the input clock signal. The selection mechanism can also cause the selected DLL to be activated and the unselected DLL(s) to be deactivated, thereby conserving power.

主权项

1. A delay locked loop circuit for a system having two modes of operation, comprising:
a first delay locked loop having a first operating frequency range, the first operating frequency range selected for a first of the two modes of operation; a second delay locked loop having a second operating frequency range, the second operating frequency range selected for a second of the two modes of operation; and a selector configured to dynamically select for output and power only one of the first and second delay locked loops, wherein the first and second frequency ranges are different, wherein the first delay locked loop is selected for the first mode of operation and the second delay lock loop is selected for the second mode of operation.