发明名称 |
Semiconductor device having at least a transistor cell with a second conductive type region surrounding a wall region and being insulated from both gate electrode and source electrode and solid state relay using same |
摘要 |
A semiconductor device includes one or more transistor cells mounted on a first conductive type silicon carbide (SiC) substrate, wherein each of the transistor cells includes a second conductive type wall region formed on a first surface of the SiC substrate, a first conductive type source region formed in the wall region, a gate electrode formed with a gate insulating film; a source electrode formed in such a way as to be brought into contact with the source region, and a drain electrode formed on a second surface of the SiC substrate. The semiconductor device further includes a second conductive type region located close to an outside of an outermost cell of the transistor cells, the second conductive type region surrounding the wall region and being insulated from both of the gate electrode and the source electrode. |
申请公布号 |
US8933394(B2) |
申请公布日期 |
2015.01.13 |
申请号 |
US201113642153 |
申请日期 |
2011.02.23 |
申请人 |
Panasonic Corporation |
发明人 |
Okada Hiroshi;Sunada Takuya;Oomori Takeshi |
分类号 |
H01J5/02;H01L29/06;H03K17/687;H01L25/16;H01L29/78;H01L29/66;H01L29/16;H03K17/785 |
主分类号 |
H01J5/02 |
代理机构 |
Renner, Otto, Boisselle & Sklar, LLP |
代理人 |
Renner, Otto, Boisselle & Sklar, LLP |
主权项 |
1. A semiconductor device comprising:
one or more transistor cells mounted on a first conductive type silicon carbide (SiC) substrate, wherein each of the transistor cells includes: a second conductive type wall region formed on a first surface of the SiC substrate, a first conductive type source region formed in the wall region, a gate electrode formed with a gate insulating film; a source electrode formed in such a way as to be brought into contact with the source region, and a drain electrode formed on a second surface of the SiC substrate; and a second conductive type region located close to an outside of an outermost cell of the transistor cells, the second conductive type region surrounding the wall region and being insulated from both of the gate electrode and the source electrode. |
地址 |
Osaka JP |