Removing scan channel limitation on semiconductor devices

摘要

A method to perform component testing by supplying test patterns to a serial input pin coupled to an IEEE 1149.6 boundary-scan cell that is associated with an IEEE 1149.6 test receiver. The test receiver is configured to operate in a scan test mode. The output from the test receiver circuit is coupled to a logic block to be scan tested. The output from the logic block is coupled to a serial output pin on the integrated circuit during scan test mode. High performance integrated circuits can use SerDes pins in a scan test mode to be scan tested without impacting mission critical signals.

主权项

1. A method to perform component testing, the method comprising:
supplying a test pattern to a serial input pin on an integrated circuit, the serial input pin being coupled to a boundary-scan cell that is associated with a test receiver; configuring the test receiver to operate in a scan test mode; coupling output of the test receiver during the scan test mode to a logic block to be scan tested; and coupling output from the logic block to a serial output pin on the integrated circuit via a scan test multiplexer when the scan test multiplexer selects the scan test mode.