System and method for controlling memory command delay

摘要

A system with a processor in communication with a memory controller in communication with a plurality of memory devices wherein one of the plurality of memory devices is interposed between the memory controller and the remaining plurality of memory devices. By programming command delay in the memory controller, the command delay coordinates the execution of the command signal across all memory devices. The processor provides control signals to the memory controller that, in response, decodes the control signals and determines the mode of operation of one or more of the memory devices. The processor is also in communication with storage media and stores data in or retrieves data from the storage media.

主权项

1. A method of operating a device comprising:
receiving data in a memory controller; determining, in the memory controller, where in a plurality of memory devices to store the data, each of the plurality of memory devices comprising programmable command and response delay units; determining in each of the plurality of memory devices a device-specific delay for command propagation and a device-specific delay for response propagation; predicting, in the memory controller, when a memory device will execute a given command based on the device specific command delay and the device-specific response delay, wherein the device-specific command propagation delay and the device-specific response delay are programmable by a processor.