| 发明名称 | State transitioning clock gating | ||
| 摘要 | An integrated circuit (IC) is described. The IC includes a clock distribution network for distributing a clock signal. The IC includes a first sequential circuit having a clock input to receive the clock signal to generate an output. The output of the first sequential circuit is coupled to an input of a first logic group comprising combinatorial logic circuitry. The IC also includes first circuitry to compare logic states of the input and the output and to inhibit the clock signal from propagating to the clock input if the logic states are the same. The IC also includes a second sequential circuit having a second clock input to receive the clock signal to generate a second output. The second output of the second sequential circuit is coupled to an input of a second logic group comprising combinatorial logic circuitry. The IC also includes second circuitry to compare logic states of the input and the output of the second sequential circuit and to inhibit the clock signal from propagating to the second sequential circuit if the logic states are the same. | ||
| 申请公布号 | US8933724(B2) | 申请公布日期 | 2015.01.13 |
| 申请号 | US201213653138 | 申请日期 | 2012.10.16 |
| 申请人 | Intel Corporation | 发明人 | Cressman John W. |
| 分类号 | G06F7/38;H03K19/177;H03K17/16;H03K19/003;H03K3/00;H03K19/00;G06F1/32 | 主分类号 | G06F7/38 |
| 代理机构 | Blakely, Sokoloff, Taylor & Zafman LLP | 代理人 | Blakely, Sokoloff, Taylor & Zafman LLP |
| 主权项 | 1. An integrated circuit (IC) comprising: a clock distribution network for distributing a clock signal; a first sequential circuit having a clock input to receive the clock signal to generate an output, the output of the first sequential circuit coupled to an input of a first logic group comprising combinatorial logic circuitry; and first circuitry to compare logic states of the input and the output and to inhibit the clock signal from propagating to the clock input if the logic states are the same; a second sequential circuit having a second clock input to receive the clock signal to generate a second output, the second output of the second sequential circuit coupled to an input of a second logic group comprising combinatorial logic circuitry; and second circuitry to compare logic states of the input and the output of the second sequential circuit and to inhibit the clock signal from propagating to the second sequential circuit if the logic states are the same. | ||
| 地址 | Santa Clara CA US | ||