Self-aligned gate electrode diffusion barriers

摘要

A self-aligned diffusion barrier may be formed by forming a first masking layer, having a vertical sidewall on a semiconductor layer, above a first portion of the semiconductor layer. A first spacer layer, including a spacer region on the vertical sidewall, may be formed above the semiconductor layer. A second portion of the semiconductor layer not covered by the first masking layer or the spacer region may then be doped. A second masking layer may then be formed over the first spacer layer and planarized to expose at least a portion of the spacer region. The spacer region may then be etched to form a notch exposing a third portion of the semiconductor layer. The third portion may then be doped with a barrier dopant. The first masking layer may be removed and a second spacer layer filling the notch may be formed. The first portion may then be doped.

主权项

1. A method of forming a self-aligned diffusion barrier between a first doped region and a second doped region, the method comprising:
forming a first masking layer above a first portion of a semiconductor layer, wherein the first masking layer comprises an end having a vertical sidewall; forming a first spacer layer above the semiconductor layer and the first masking layer, wherein the spacer layer comprises a spacer region on the vertical sidewall; doping a second portion of the semiconductor layer not covered by the first masking layer and not covered by the spacer region; forming a second masking layer over the first spacer layer; planarizing the second masking layer to expose at least a portion of the spacer region; etching the exposed portion of the spacer region to form a notch exposing a third portion of the semiconductor layer between the first portion and the second portion; doping the third portion of the semiconductor layer with a barrier dopant; removing the first masking layer; forming a second spacer layer over the second masking layer, wherein the second spacer layer fills the notch; and doping the first portion of the semiconductor layer.