System and method for performing scan test

摘要

A system for performing a scan test on an integrated circuit such as a System on a Chip (SoC) that may be packaged in different package types and with different features enabled includes a bypass-signal generator and a first scan-bypass circuit. The bypass-signal generator generates a first bypass signal based on chip package information. The first bypass signal indicates whether a first scan chain associated with a first non-common circuit block of the SoC is to be bypassed. The first scan chain is bypassed in response to the first bypass signal. By enabling partial scan testing based on package information, unintentional yield loss caused by a full scan test determining an SoC is faulty can be avoided.

主权项

1. A system for performing a scan test and memory built-in self test (BIST) on an integrated circuit (IC), the system comprising:
a bypass-signal generator that generates a first bypass signal based on a chip package information, the first bypass signal indicating whether a first scan chain associated with a first non-common functional circuit block of the IC is to be bypassed; and a first scan-bypass circuit, connected to the bypass-signal generator and receiving the first bypass signal, for bypassing the first scan chain in response to the first bypass signal; a first built-in self test (BIST) controller associated with a first non-common memory block of the IC; and a first BIST-bypass circuit, connected to the bypass-signal generator and receiving the first bypass signal, for gating off an output of the first BIST controller in response to the first bypass signal.