发明名称 Computer aided design apparatus, computer aided design program, computer aided design method for a semiconductor device and method of manufacturing a semiconductor circuit based on characteristic value and simulation parameter
摘要 A simulation instructing unit instructs a simulation unit, which generates signal characteristics, to generate the signal characteristics. A characteristic value extracting unit extracts, from the signal characteristics, characteristic values for distinguishing between a signal characteristic generated by setting a first simulation parameter and a signal characteristic generated by a second simulation parameter. A simulation parameter determining unit determines a first mapping relationship from the characteristic values to the simulation parameters with the characteristic values obtained by setting a plurality of set values in the simulation parameters and with the set values.
申请公布号 US8935146(B2) 申请公布日期 2015.01.13
申请号 US200812042059 申请日期 2008.03.04
申请人 Fujitsu Semiconductor Limited 发明人 Arimoto Hiroshi;Yamaguchi Seiichiro
分类号 G06F17/50 主分类号 G06F17/50
代理机构 Westerman, Hattori, Daniels & Adrian, LLP 代理人 Westerman, Hattori, Daniels & Adrian, LLP
主权项 1. A computer aided design apparatus, comprising: a memory; and a processor connected to the memory, wherein the processor is configured to operate in accordance with executable instructions that, when executed, cause the processor to perform: generating a signal characteristic of a transistor by simulating an operation of the transistor with simulation parameters using the processor; extracting from the signal characteristic, characteristic values for distinguishing between a first signal characteristic generated by setting first values in the simulation parameter and a second signal characteristic generated by setting second values in the simulation parameters, at least any one of the second values being different from the first values, the characteristic values being different from the simulation parameters; determining a first mapping relationship to the simulation parameters from the characteristic values with a combination of the characteristic values and set values, the characteristic values being respectively obtained by simulating the operation of the transistor with a plurality of combinations of the set values which are assigned to the simulation parameters using the processor, the first mapping relationship being mapping from a set of the characteristic values to a set of the set values which are assigned to the simulation parameters; obtaining a third mapping relationship to the characteristic values from layout information by modeling and a calculation on the basis of plural combinations of information showing a relationship between the layout information of an area in which the transistor is formed and the characteristic values of the transistor; and obtaining a fourth mapping relationship defined as mapping to the simulation parameters from the layout information by substituting a value obtained with application of the third mapping relationship being applied to the layout information into the characteristic value defined as an input value of the first mapping relationship, wherein the determining of the first mapping relationship includes: obtaining a second mapping relationship to the characteristic values from the simulation parameters, the second mapping relationship being expressed by a polynomial expression of simulation parameters, by determining one or more coefficients of the polynomial expression to fit the polynomial expression to the combination of the set values and the characteristic values obtained by the simulating; and transforming inversely the second mapping relationship into an inverse mapping of the polynomial expression, the inverse mapping being expressing the first mapping relationship.
地址 Yokohama JP