Bit set modes for a resistive sense memory cell array

摘要

Various embodiments of the present invention are generally directed to a method and apparatus for providing different bit set modes for a resistive sense memory (RSM) array, such as a spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM) array. In accordance with some embodiments, a group of RSM cells in a non-volatile semiconductor memory array is identified for application of a bit set operation. A bit set value is selected from a plurality of bit set values each separately writable to the RSM cells to place said cells in a selected resistive state. The selected bit set value is thereafter written to at least a portion of the RSM cells in the identified group.

主权项

1. A data storage device, comprising:
an array of memory cells arranged into rows and columns, each memory cell comprising a switching device in series with a resistive random access memory (RRAM) element; and a controller configured to execute a first bit set operation comprising placing a first group of the memory cells in a lowest resistance state and to subsequently direct a writing of first user data from the host device to the array by overwriting the lowest resistance state of at least one and less than all of the first group of the memory cells, and to execute a second bit set operation comprising placing a second group of the memory cells in a highest resistance state and to subsequently direct a writing of second user data from the host device to the array by overwriting the highest resistance state of at least one and less than all of the second group of the memory cells.