Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure

摘要

Sophisticated gate stacks including a high-k dielectric material and a metal-containing electrode material may be covered by a protection liner, such as a silicon nitride liner, which may be maintained throughout the entire manufacturing sequence at the bottom of the gate stacks. For this purpose, a mask material may be applied prior to removing cap materials and spacer layers that may be used for encapsulating the gate stacks during the selective epitaxial growth of a strain-inducing semiconductor alloy. Consequently, enhanced integrity may be maintained throughout the entire manufacturing sequence, while at the same time one or more lithography processes may be avoided.

主权项

1. A method of forming a gate electrode structure of a transistor, the method comprising:
forming a protection liner on sidewalls of a gate stack, said gate stack being formed above a semiconductor layer and comprising a high-k dielectric gate insulation layer, a metal-containing electrode material formed on said high-k dielectric gate insulation layer and a cap layer; forming a mask material above said semiconductor layer so as to cover said protection liner at least at a bottom of said gate stack; removing said cap layer in the presence of said mask material; and forming a semiconductor alloy in said semiconductor layer with an offset from said gate stack that is determined by a spacer structure formed on said protection liner at the sidewalls of said gate stack.