| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a clock signal generating circuit in which power consumption is reduced as a whole by reducing the power consumption of a multiplying circuit 4 when any clock signal whose frequency is unstable is not outputted. SOLUTION: This circuit is provided with a clock signal oscillating circuit 1 for outputting a clock signal, a multiplying circuit 4 for multiplying the clock signal, and for generating the multiplied clock signal, a counter 5 for counting the clock signal just after the oscillation of the clock signal is started by the clock signal oscillating circuit 1, and for outputting an operation start signal, when the count value reaches a preliminarily set value, a central arithmetic processing part 3, and a multiplied clock signal output control part 9. The multiplying circuit 4 starts the multiplying operating of the clock signal when the operating start signal is supplied, and the central arithmetic processing part 3 starts the processing operation when the operation start signal is supplied, and the multiplied clock signal output control part 9 transmits and supplies the multiplied clock signal supplied from the multiplying circuit 4 to a use circuit when the operation start signal is supplied.</p> |
