发明名称 SYSTEM FOR PROVIDING TRACE DATA IN A DATA PROCESSOR HAVING A PIPELINED ARCHITECTURE
摘要 The invention is a method and system for providing trace data in a pipelined data processor. Aspects of the invention include providing a trace pipeline in parallel to the execution pipeline, providing trace information on whether conditional instructions complete or not, providing trace information on the interrupt status of the processor, replacing instructions in the processor with functionally equivalent instructions that also produce trace information and modifying the scheduling of instructions in the processor based on the occupancy of a trace output buffer.
申请公布号 US2015012728(A1) 申请公布日期 2015.01.08
申请号 US201414271886 申请日期 2014.05.07
申请人 Imagination Technologies Limited 发明人 Isherwood Robert Graham;Oliver Ian;Webber Andrew David
分类号 G06F9/38;G06F9/48;G06F9/30 主分类号 G06F9/38
代理机构 代理人
主权项
地址 Kings Langley GB