发明名称 Configurable data processing system based on a hybrid data and control driven processing architecture
摘要 A data processing system comprising a plurality of data inputs and of data outputs for processing input data and providing processed data to a data output. The system comprises a plurality of data processing hardware units, each being configured to process data within a predetermined latency and according to a data processing task of a predetermined type. The system further comprises a memory for storing a predetermined latency for each of the data processing hardware units and a controller configured to determine a type of a data processing task to be executed as a function of a source of data to be processed or of a destination of processed data and further configured to select one data processing hardware unit as a function of the determined type of the task to be executed and of latency constraints associated with the task to be executed.
申请公布号 US2015012676(A1) 申请公布日期 2015.01.08
申请号 US201414320361 申请日期 2014.06.30
申请人 CANON KABUSHIKI KAISHA 发明人 CLOSSET Arnaud;ROUSSEAU Pascal
分类号 G06F13/16 主分类号 G06F13/16
代理机构 代理人
主权项 1. A data processing system comprising a plurality of data inputs and of data outputs for processing system input data and providing processed data to a data output, the data processing system comprising: a plurality of data processing hardware units, each data processing hardware unit being configured to process data within a predetermined latency and according to a data processing task of a predetermined type, to provide an item of processed data; a memory for storing the predetermined latency for each of the data processing hardware units; and a controller configured to determine a type of a data processing task to be executed as a function of a source of data to be processed or of a destination of processed data and further configured to select one data processing hardware unit as a function of the determined type of the data processing task to be executed and of latency constraints associated with the data processing task to be executed taking into account the predetermined latencies stored in the memory, at least one source of data to be processed being linked to at least one data input of the plurality of data inputs and at least one destination of processed data being linked to at least one data output of the plurality of data outputs.
地址 Tokyo JP