| 摘要 |
<p>Provided is an array substrate row driving circuit. The driving circuit comprises a plurality of array substrate row driving units. An nth stage array substrate row driving unit of the array substrate row driving circuit is provided with an (n-2)th stage signal input end (21), an (n+2)th stage signal input end (22), a clock signal first input end (23), a clock signal second input end (24), a first low level input end (25), a second low level input end (26), a first output end (27), and a second output end (28). The nth level array substrate row driving unit also comprises a pull-up driving unit (32), a pull-up unit (34), and a first pull-down unit (36), a second pull-down unit (37), and a third pull-down unit (38). A second low level signal is added, and a voltage difference Vgs between a gate and a source of a thin-film transistor of a first output end is lowed by using a second low level, thereby making a leakage current of the thin-film transistor relatively low, and accordingly, the control is precise.</p> |
