| 发明名称 |
DIGITAL SELF-GATED BINARY COUNTER |
| 摘要 |
An n-bit counter is formed from cascading counter sub-modules. The counter includes combinatorial control logic coupled to a lower order counter sub-module. The control logic is arranged to clock gate at least one higher order counter sub-module dependent on a logical combination of outputs of the lower order counter sub-module and where the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output. |
| 申请公布号 |
US2015010124(A1) |
申请公布日期 |
2015.01.08 |
| 申请号 |
US201313935552 |
申请日期 |
2013.07.04 |
| 申请人 |
Gupta Naman;Agarwal Amol;Goyal Gaurav |
发明人 |
Gupta Naman;Agarwal Amol;Goyal Gaurav |
| 分类号 |
H03K23/40 |
主分类号 |
H03K23/40 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. An n-bit counter circuit formed from a plurality of cascading counter sub-modules, comprising:
combinatorial control logic coupled to a lower order counter sub-module of the counter circuit, wherein the control logic is arranged to clock gate at least one higher order counter sub-module of the counter circuit dependent on a logical combination of outputs of the lower order counter sub-module; and wherein the control logic uses pipelining to store at least one previous control logic output for use in determining a later control logic output. |
| 地址 |
Delhi IN |
