COMPENSATED WELL ESD DIODES WITH REDUCED CAPACITANCE

摘要

An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.

主权项

1. An integrated circuit, comprising:
a p-type substrate; a pwell formed in said p-type substrate where doping of said pwell is higher than doping of said p-type substrate; an NMOS transistor with a NMOS transistor gate and with N+ doped deep source and drain diffusions formed in a pwell on said p-type substrate; a first nwell formed in said p-type substrate; a PMOS transistor with a PMOS transistor gate and with P+ doped deep source and drain diffusions formed in said first nwell; an ESD diode gate which isolates a N+ deep diffusion from a P+ deep diffusion where said N+ deep diffusion and said N+ doped deep source and drain diffusion doping concentrations are equal and where said P+ deep diffusion and said P+ deep source and drain diffusion doping concentrations are equal; a low capacitance GS ESD diode selected from the group consisting of:
a diode formed between said N+ deep diffusion and said p-type substratea diode formed between a second nwell and an isolated pwell where said isolate pwell is formed in said second nwell;a diode formed between a counter doped nwell N− diffusion and said p-type substrate; anda diode formed between said counter doped nwell N− diffusion and said isolated pwell where said N+ deep diffusion is a cathode of said low capacitance GS ESD diode; and where said P+ deep diffusion is an anode of said low capacitance GS ESD diode.