| 摘要 |
A first connection wire (210) is formed by way of a lower layer wire near a semiconductor element, and a second connection wire (220) is formed by way of an upper layer wire far from the semiconductor element. In addition, extending through a silicon substrate (100), a first aperture portion reaching the first connection wire (210) and a second aperture portion reaching the second connection wire (220) are formed from the rear face of the silicon substrate (100), and subsequently, a first through silicon via (230) and a second through silicon via (240) are formed in the interior of each of the first aperture portion and the second aperture portion, respectively. As a result, it is possible to form the first through silicon via (230) for signal propagation connecting to the first connection wire (210), and the second through silicon via (240), for clock supply and power supply, connecting to the second connection wire (220), and therefore, it is possible to provide a semiconductor device achieving low parasitic resistance and significant allowable current. |
