TESTING OF NON-VOLATILE MEMORY ARRAYS

摘要

A method of testing non-volatile memory arrays. A first test stage including at least a first stage read uses a first step size for setting current for BCC testing and/or voltage for VT testing for reading at least some memory cells. A second test stage including at least one second stage read uses an adjusted step size less in magnitude than the first step size for reading at least some memory cells. Provided no bit pattern match by the second test stage and/or the adjusted step size does not meet a predetermined minimum resolution (PMR), one or more additional test stages including additional array searching are added using a fixed step size less in magnitude than the adjusted step size including at least one read until a final read determines the predetermined bit pattern is matched and a fixed step size for the final read meets the PMR.

主权项

1. A method of testing a non-volatile memory array including a plurality of memory cells, comprising:
initializing said plurality of memory cells to a predetermined bit pattern, and performing multi-stage testing including bit cell current (BCC) testing and/or threshold voltage (VT) testing for said plurality of memory cells, said multi-stage testing having a plurality of test stages including:
performing a first test stage including first array searching including at least one first stage read using a first step size for setting reference current for said BCC testing and/or voltage for said VT testing for reading at least some of the plurality of memory cells;performing a second test stage including second array searching including at least one second stage read using an adjusted step size that is less in magnitude than (<) said first step size for setting reference current for said BCC testing and/or voltage for said VT testing for reading at least some of the plurality of memory cells, andprovided said predetermined bit pattern is not matched by said second test stage and/or said adjusted step size does not meet a predetermined minimum resolution (PMR), adding one or more additional test stages including additional array searching using a fixed step size less in magnitude than said adjusted step size for setting reference current for said BCC testing and/or voltage for said VT testing including at least one read until a final read determines said predetermined bit pattern is matched and a fixed step size used for said final read meets said PMR.