CALIBRATION OF CLOCK PATH MISMATCHES BETWEEN DATA AND ERROR SLICER

摘要

Embodiments include systems and methods for calibrating effective clock path mismatches in a receiver circuit. For example, a serializer/deserializer (SERDES) circuit includes a data slicer that generates data sampler decisions by sampling an input signal according to a clocking signal, and an error slicer that generates error slicer samples by sampling the input signal according to the clocking signal. Each of the data slicer and error slicer has an associated clock path delay, and the delays are typically different (e.g., due to manufacturing differences). A calibrator performs iteratively shifted sampling and comparing of the data sampler decisions and the error slicer samples over a plurality of clocking locations to determine an effective clock path mismatch. The calibrator can then determine and apply a clocking offset to the data slicer and/or the error slicer to effectively shift data and error sampling, thereby compensating for the effective clock path mismatch.

主权项

1. A system for determining a bit sequence from an input signal, the system comprising:
a data slicing subsystem that operates to generate data sampler decisions by sampling the input signal according to a clocking signal with respect to a reference level; an error slicing subsystem that operates to generate error slicer samples by sampling the input signal according to the clocking signal with respect to an estimated signal value; and a calibration subsystem, in communication with the data slicing subsystem and the error slicing subsystem, that operates to:
compare the data sampler decisions with the error slicer samples to determine an effective clock mismatch window between the data slicing subsystem and the error slicing subsystem; andapply a clocking offset to at least one of the data slicing subsystem or the error slicing subsystem as a function of the determined effective clock mismatch window.