| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve a time resolution in a high-output clock phase by setting an operation clock in a comparatively low frequency. <P>SOLUTION: A digital PLL device has an input-signal timing detector 2 detecting the phase of an input signal at a time-resolution unit obtained by dividing one period into N, and outputting an input-signal timing data having a value corresponding to the result of the detection at every one period; and an output-clock generator 5 outputting an output-clock timing data having the value corresponding to a virtual output-clock phase, as the phase of a virtual output clock changed at the time-resolution unit at every one period in response to a frequency control data. The digital PLL device further has a phase-difference detecting section 3 detecting the input signal and the virtual output-clock phase from the input-signal timing data and the output-clock timing data, and outputting a phase-difference signal having the value corresponding to the result of the detection; and a frequency control section 4 changing the frequency-control data in response to the phase-difference signal. <P>COPYRIGHT: (C)2006,JPO&NCIPI |
