| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To obtain a low power consumption burst CDR circuit having a high processing speed. <P>SOLUTION: A burst CDR circuit has: an N-phase clock generation circuit 2 generating an N-phase clock; an N-phase clock sampling circuit 3 sampling a burst signal by using the N-phase clock; a simple phase selection circuit 4 extracting a simple center phase from an EXOR operation value of sampling data associated with an adjacent phase; a first DEMUX circuit 5 performing parallel development of data associated with the simple center phase; a center phase integration and extraction circuit 6 integrating the parallel-developed data n times and outputting parity number data indicating parity of a center phase number; a selector circuit 7 outputting data corresponding to the parity number data based on the sampling data associated with the adjacent phase; a second DEMUX circuit 8 performing parallel development of the data from the selector circuit; and an optimum phase data high-accuracy extraction circuit 9 integrating the parallel-developed data m times and outputting sampling data at the most-distant phase from a data edge phase. <P>COPYRIGHT: (C)2013,JPO&INPIT</p> |
