发明名称 TRANSMITTER, ENCODING DEVICE, RECEIVER, AND DECODING DEVICE
摘要 A decoding device inputs: a redundant bit generated between data blocks contained in each of sets obtained by combining a plurality of data blocks obtained by dividing a signal bit string; and a code block obtained by error-correction-encoding the data blocks; so as to make the bit string in the code block to be an input. The decoding device calculates signal bit reliability information. Moreover, the decoding device repeats a process to use the calculated reliability information as an input to calculate new reliability information relating to a signal bit in the data block subjected to the error correction encoding into a code block. Furthermore, the decoding device repeats a process to calculate inter-block reliability information indicating the reliability of the signal bit which has contributed to generation of the redundant bit and input the inter-block reliability information, as reliability information relating to the signal bit, into an in-block repetition calculation unit in accordance with the redundant bit generated between the data blocks contained in the respective sets and the reliability information repeatedly calculated by the in-block repetition calculation unit.
申请公布号 EP2472726(A4) 申请公布日期 2015.01.07
申请号 EP20090848708 申请日期 2009.08.25
申请人 FUJITSU LIMITED 发明人 ITO, AKIRA
分类号 H03M13/29;H03M13/09;H03M13/11 主分类号 H03M13/29
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