发明名称 WIRING SUBSTRATE
摘要 <p>The present invention relates to a wiring substrate. A wiring substrate (A) includes: an insulating layer (3) including a lower layer conductor (5) on the lower surface thereof; a plurality of semiconductor element connection pads (10) arranged in a lattice pattern in a semiconductor element mounting part (1a) having a quadrangular shape on the insulating layer (3); a via hole (7a) formed in the insulating layer (3) below each of the semiconductor element connection pads (10) with the lower layer conductor (5) as a bottom surface; and a via conductor (9a) filled in the via hole (7a) and formed integrally with each of the semiconductor element connection pads (10). The wiring substrate (A) includes: a reinforcing via hole (7b) formed in the insulating layer (3) in an outer region outside an arrangement region (1b) of the semiconductor element connection pads (10) in corners of the semiconductor element mounting part (1a) with the lower layer conductor (5) as a bottom surface; and a reinforcing via conductor (9b) formed in the reinforcing via hole (7b).</p>
申请公布号 KR20150002493(A) 申请公布日期 2015.01.07
申请号 KR20140077882 申请日期 2014.06.25
申请人 KYOCERA SLC TECHNOLOGIES CORPORATION 发明人 IINO MASAKAZU;FUJISAKI TERUYA;OYOSHI TAKAFUMI
分类号 H01L21/60;H01L21/28 主分类号 H01L21/60
代理机构 代理人
主权项
地址