RECONFIGURABLE SIMD PROCESSOR AND ITS EXECUTION CONTROL METHOD

摘要

A reconfigurable SIMD processor capable of flexibly dealing with subjects for processing of differing characteristics by only small increase in circuit size, in comparison with a conventional configuration, while the performance of the processor in its entirety is improved, is disclosed. A method for reconfigurable SIMD processing is also disclosed. A GPR 10 of each general purpose register of a PE-1 is initialized to the number of cycles needed for division, while its GPR 11 is initialized to 1, its GPR 20 is initialized to a dividend and its GPR 21 is initialized to a divisor. The GPR 21 is subtracted from the GPR 20 by an adder/subtractor Add/ Sub -1, and the number of cycles needed for division is counted. The GPR 21 is subtracted from the GPR 20 by an adder/subtractor Add/Sub -2 until the count value reaches a predetermined value. In case the result of the subtraction is positive, the GPR 20 is updated by a value corresponding to the result of the subtraction shifted towards left one bit. In case the result of the subtraction is negative, the GPR 20 is updated by a value corresponding to the GPR 20 shifted towards left one bit. The GPR 22 is updated by a bit string corresponding to the GPR 22, the MSB of which has been removed and to the LSB of which is added a value inverted from the MSB of the result of the subtraction.