发明名称 SYSTEM IN PACKAGE, LOGIC IC, AND MEMORY IC
摘要 <p><P>PROBLEM TO BE SOLVED: To achieve an SiP capable of specifying a failure part of bonding connection, without increasing the number of terminals. <P>SOLUTION: In this SiP1, IC2 and IC3 are mounted to a package 1, and the terminals of the IC2 and IC3 are interconnected by a bonding wire. The IC2 comprises a test mode setting circuit 13, output switching circuits 16A-16C disposed corresponding to respective terminals 20A-20C of a first group, input switching circuits 18A-18C and 19A-19C disposed corresponding to respective terminals 21A-21C of a second group, and determination circuits 15A-15C for determining the input test signal. The IC3 comprises a test mode setting circuit 32, input circuits 35A-35C disposed corresponding to respective terminals 33A-33C of the first group, and output switching circuits 37A-37C and 38A-38C disposed corresponding to respective terminals 34A-34C of the second group; and during the test mode, the output switching circuits of the IC2 reverse a first-stage test signal or the front-stage input test signal and output it, and the output switching circuits of the IC3 reverse and output the front-stage input test signal. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009002837(A) 申请公布日期 2009.01.08
申请号 JP20070165021 申请日期 2007.06.22
申请人 FUJITSU MICROELECTRONICS LTD 发明人 HORISAKI YASUNOBU
分类号 G01R31/28;G11C11/401;G11C29/02;H01L21/822;H01L27/04 主分类号 G01R31/28
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