发明名称 レギュレータ回路
摘要 There is provided a regulator circuit capable of increasing the capacity of the output transistor for supplying current, stably generating an internal power supply voltage and adapting to the reduction of a power supply voltage. The regulator circuit includes an output transistor which is supplied with an external power supply voltage and supplies dropped voltage to an internal circuit, a differential amplifier for outputting a gate potential applied to the gate of the output transistor, a reference voltage generating circuit for supplying a reference voltage to the differential amplifier, and a cut-off transistor for turning off the output transistor to stop supplying power to the internal circuit. The output transistor is comprised of a depression NMOS transistor whose threshold voltage is a negative voltage. The regulator circuit further includes substrate potential control means for controlling the substrate potential of the depression NMOS transistor.
申请公布号 JP5649857(B2) 申请公布日期 2015.01.07
申请号 JP20100140449 申请日期 2010.06.21
申请人 ルネサスエレクトロニクス株式会社 发明人 野谷 宏美
分类号 G05F1/56 主分类号 G05F1/56
代理机构 代理人
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