发明名称 サイドチャネル攻撃に対する素数生成の保護
摘要 #CMT# #/CMT# The method involves testing primality with respect to prime numbers of one set of consecutive prime numbers, for each candidate number. The order of application of tests is modified from one prime number generation to another. #CMT# : #/CMT# An independent claim is included for electronic circuit. #CMT#USE : #/CMT# Method for protecting generation of prime numbers in electronic circuit (claimed) for smart card. #CMT#ADVANTAGE : #/CMT# The generation of prime numbers in electronic circuit can be protected reliably. #CMT#DESCRIPTION OF DRAWINGS : #/CMT# The drawing shows a block diagram of the electronic circuit. 1 : Electronic circuit 11 : Processing unit 13 : Non-volatile memory 14 : Volatile memory 15 : Input/output interface circuits.
申请公布号 JP5648177(B2) 申请公布日期 2015.01.07
申请号 JP20100201184 申请日期 2010.09.08
申请人 发明人
分类号 G09C1/00 主分类号 G09C1/00
代理机构 代理人
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