| 发明名称 | Clock generation circuit, successive comparison A/D converter, and integrated circuit device | ||
| 摘要 | A clock generation circuit includes a first loop circuit configured to generate a first clock, and a second loop circuit configured to generate a second clock including a period different from a period of the first clock. A fluctuation in an amount of delay of the first clock is adjusted based on the second clock and the first clock including the period adjusted is output. | ||
| 申请公布号 | US9369137(B2) | 申请公布日期 | 2016.06.14 |
| 申请号 | US201514880927 | 申请日期 | 2015.10.12 |
| 申请人 | SOCIONEXT INC. | 发明人 | Masuko Shuichi |
| 分类号 | H03M1/06;H03L7/081;H03M1/46 | 主分类号 | H03M1/06 |
| 代理机构 | Arent Fox LLP | 代理人 | Arent Fox LLP |
| 主权项 | 1. A clock generation circuit comprising: a first loop circuit configured to generate a first clock; and a second loop circuit configured to generate a second clock including a period different from a period of the first clock, wherein a fluctuation in an amount of delay of the first clock is adjusted based on the second clock and the first clock including the period adjusted is output. | ||
| 地址 | Yokohama JP | ||