发明名称 試験装置及び試験方法
摘要 According to one embodiment, a test apparatus includes a reception buffer configured to store uplink data, a transmission buffer configured to store downlink data, an arithmetic processing module configured to execute reception arithmetic processing on the uplink data read from the reception buffer, and to execute transmission arithmetic processing to generate downlink data and store the generated downlink data in the transmission buffer, and a management module configured to provide, under a first predetermined condition, the arithmetic processing module with a first instruction to execute the reception arithmetic processing, and to provide, under a second predetermined condition, the transmitting/receiving module with a second instruction to transmit the downlink data stored in the transmission buffer.
申请公布号 JP5934276(B2) 申请公布日期 2016.06.15
申请号 JP20140068951 申请日期 2014.03.28
申请人 アンリツ株式会社 发明人 滝沢 圭祐;橋本 礼一
分类号 H04B17/17;H04B17/29;H04M1/24 主分类号 H04B17/17
代理机构 代理人
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