Wireless physiological sensor patches and systems

摘要

The present invention provides methods, devices, and systems for wireless physiological sensor patches and systems which incorporate these patches. The systems and methods utilize a structure where the processing is distributed asymmetrically on the two or more types of ASIC chips that are designed to work together. The invention also relates to systems comprising two or more ASIC chips designed for use in physiological sensing wherein the ASIC chips are designed to work together to achieve high wireless link reliability/security, low power dissipation, compactness, low cost and support a variety of sensors for sensing various physiological parameters.

主权项

1. A system for measuring physiological signals, comprising:
(a) a patch-ASIC chip adapted for incorporation into a physiological signal monitoring patch comprising a sensor interface, a processor coupled to the sensor interface, a memory element coupled to the processor, a radio comprising an ultra wideband (UWB) transmitter and a narrowband receiver coupled to the memory element that transmits sensor data via the UWB transmitter to a base-ASIC chip and/or a gate-ASIC chip and receives instructions from the base-ASIC chip and/or gate-ASIC chip via the narrowband receiver, and power management circuits that coordinate power on the patch-ASIC chip; (b) the gate-ASIC chip comprising a processor that processes sensor data, a memory element coupled to the processor, a radio transceiver coupled to the processor that directs communication between the patch-ASIC chip and the base-ASIC chip, and power management circuits that coordinate power on the gate-ASIC chip; and (c) the base-ASIC chip comprising a processor that processes sensor data, a memory element coupled to the processor, a radio comprising a UWB receiver and a narrowband transmitter coupled to the memory element that transmits said instructions to the patch-ASIC chip and/or the gate-ASIC chip via the narrowband transmitter and receives said sensor data from said patch-ASIC chip and/or said gate-ASIC chip via the UWB receiver, power management circuits that coordinate power on the base-ASIC chip, and a host interface through which the base-ASIC chip communicates with a host device, wherein the base-ASIC chip is programmed to use more processing resources than the patch-ASIC chip.