Digital circuit testable through two pins

摘要

A method for scan-testing of an integrated circuit includes the following steps carried out by the circuit itself: upon powering on of the circuit, watching for bit sequences applied to a use pin configured for receiving serial data from the exterior at the rate of a clock signal applied to a clock pin; configuring the circuit in a test mode when a bit sequence is identified as a test initialization sequence; connecting latches of the circuit in a shift register configuration, and connecting the shift register for receiving a test vector in series from the use pin; switching the transfer direction of the use pin to the output mode for providing to the exterior serial data at the rate of the clock signal; and connecting the shift register for providing its content, as a test result set, in series on the use pin.

主权项

1. A method, comprising:
responding to powering on of an integrated circuit by configuring a use pin of the integrated circuit to receive serial data at a rate of a clock signal applied to a clock pin of the integrated circuit; determining whether a test initialization bit sequence is received on the use pin; and when it is determined that the test initialization bit sequence was received on the use pin, operating the integrated circuit in a test mode, the operating including:
configuring a set of latches of the integrated circuit in a shift register configuration to receive a test vector in series from the use pin;switching a transfer direction of the use pin to an output mode to output serial data at the rate of the clock signal; andcoupling the set of latches in the shift register configuration to the use pin to output a test result set in series on the use pin, the responding, the determining and the operating the integrated circuit in the test mode being performed by the integrated circuit.