Methodology on developing metal fill as library device

摘要

A methodology for developing metal fill as a library device and, in particular, a method of generating a model of the effects (e.g., capacitance) of metal fills in an integrated circuit and a design structure is disclosed. The method is implemented on a computing device and includes generating a model for effects of metal fill in an integrated circuit. The metal fill model is generated prior to completion of a layout design for the integrated circuit.

主权项

1. A method implemented on a computing device, comprising:
obtaining, by the computing device, parameters of an integrated circuit; generating, by the computing device, a p-cell from the parameters; providing, by the computing device, model effects of the metal fill in the integrated circuit by using hierarchical compact model calls to component metal fills based on generated placement of the metal fill obtained in the p-cell; and performing, by the computing device, a Monte Carlo enabled process to determine different effects based on process variations of the integrated circuit, wherein:
the metal fill is comprised of a plurality of metal fill shapes;the model effects of the metal fill include a resistance and capacitance network representative of the metal fill, which is used to place the metal fill in open spaces between metal lines;the resistance depends on sizes and shapes of the metal fill shapes; andthe capacitance depends on the spacing of the metal fill shapes.