Array substrate for liquid crystal display and manufacturing method thereof

摘要

An array substrate for a liquid crystal display (LCD) and manufacturing method thereof are provided. The array substrate for a liquid crystal display (LCD) includes: a substrate, including: a gate electrode, a pixel electrode, and a common electrode, a gate pad formed on the substrate, and connected to the gate electrode, a gate insulating layer formed on the gate pad, a first protective layer formed on the gate insulating layer, a second protective layer formed on the first protective layer, a first metal layer formed on the second protective layer, and connected to the gate pad through a first contact hole which exposes the gate pad, a third protective layer formed on the first metal layer and the second protective layer, and a second metal layer formed on the third protective layer, and connected to the first metal layer through a second contact hole which exposes the first metal layer.

主权项

1. An array substrate for a liquid crystal display (LCD), comprising:
a substrate, comprising:
a gate electrode;a pixel electrode configured to receive a data signal; anda common electrode configured to receive a common voltage,wherein the gate electrode, the pixel electrode, and the common electrode are formed on a pixel area defined on the substrate; a gate pad formed on a gate pad area of the substrate, such that the gate pad is disposed in a same layer as the gate electrode, the gate pad being connected to the gate electrode; a gate insulating layer covering the gate pad and the gate electrode; a first protective layer formed on the gate insulating layer; a second protective layer formed on the first protective layer; a first metal layer formed on the second protective layer corresponding to the gate pad area, and connected to the gate pad through a first contact hole which exposes the gate pad; a third protective layer covering the pixel electrode, the first metal layer, and the second protective layer; and a second metal layer formed on the third protective layer corresponding to the gate pad area, and connected to the first metal layer through a second contact hole which exposes the first metal layer, wherein the first metal layer is formed on a same plane as the pixel electrode, and wherein the second metal layer is formed on a same plane as the common electrode.