Integrated multiply and divide circuit

摘要

The principles of the present invention relate to a multiply and divide circuit configured to interactively multiply and/or divide. The circuit may handle signed and unsigned values. The circuit comprises an instruction register configured to store a multiply or divide instruction, at one input register configured to store the multiply or divide operands, an Arithmetic Logic Unit (“ALU”) configured to add provided values, and configuration circuitry. The configuration circuitry responds to the instructions and performs the multiply or divide operation by iteratively providing values to the ALU.

主权项

1. A circuit capable of multiplication and division, the circuit comprising:
an instruction register configured to store an instruction to perform an operation, the circuit being configured to support instructions for operations that include at least a multiply operation, a divide operation, and a combined multiply and divide operation; an input register configured to store first and second operands of the operation; an adding unit including one or more adders, the adding unit configured to add two non-constant input values and a carry-over bit, wherein at least one of the non-constant input values is at least a portion of one of the first and second operands of the operation; and configuration circuitry configured to iteratively provide the two non-constant input values to the adding unit in response to the instruction, the configuration circuitry including:
a first multiplexer for selecting a c-value to provide to the adding unit as the carry-over bit based on whether the first operand is signed or unsigned and the operation being performed;a second multiplexer configured to provide an a-value, the second multiplexer being configured to select the a-value to provide from a plurality of potential a-values, the a-value being selected based on the operation being performed and the plurality of potential a-values that include a shifted and extended first operand, an extended second operand, a signed extended second operand, and previous outputs of the adding unit;a third multiplexer configured to select the a-value or an inverse of the a-value to provide to the adding unit as one of the two non-constant input values based on whether the first operand is signed or unsigned and the operation being performed;a fourth multiplexer configured to select a b-value to provide to the adding unit as another of the two non-constant input values based on the operation being performed, the b-value being selected from a plurality of potential b-values based on the previous outputs of the adding unit;a fifth multiplexer that receives a first portion of the output of the adding unit at a first fifth multiplexer input port and a second portion of the output of the adding unit at a second fifth multiplexer input port; anda sixth multiplexer that receives the first portion of the output of the adding unit at a first sixth multiplexer input port.