Method and apparatus for supporting low-latency external memory interfaces for integrated circuits

摘要

An external memory interface includes an input/output (IO) logic unit operable to convert a rate of data from a first rate corresponding to a memory controller/schedule unit to a second rate corresponding to an external memory device. The external memory interface also includes a latency adjustment unit, operating in a timing domain of the memory controller/schedule unit, operable to add between 1 to [(second rate/first rate)−1] cycles of latency of the second rate.

主权项

1. An external memory interface comprising:
an input/output (IO) logic unit that converts a first data rate corresponding to a memory controller/schedule unit to a second data rate corresponding to an external memory device; and a latency adjustment unit, operating in a timing domain of the memory controller/schedule unit, that adds between 0 and [(the second data rate/the first data rate)−1] cycles of latency, inclusively, at the second data rate, wherein the second data rate is greater than the first data rate.