| 发明名称 | Programmable delay generator and cascaded interpolator | ||
| 摘要 | A programmable delay generator and a cascaded interpolator are provided. The cascaded interpolator includes a set of interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase. | ||
| 申请公布号 | US8928384(B2) | 申请公布日期 | 2015.01.06 |
| 申请号 | US201314018034 | 申请日期 | 2013.09.04 |
| 申请人 | International Business Machines Corporation | 发明人 | Rylov Sergey V. |
| 分类号 | H03H11/26 | 主分类号 | H03H11/26 |
| 代理机构 | Tutunjian & Bitetto, P.C. | 代理人 | Tutunjian & Bitetto, P.C. ;Dougherty Anne V. |
| 主权项 | 1. A cascaded interpolator, comprising: a plurality of single-bit interpolator stages, each having two signal inputs and two signal outputs, configured to receive two input signals having two different phases and to generate therefrom two output signals that have a phase separation equal to a fraction of a phase separation of the two input signals, each of said single-bit interpolator stages comprising a 2:1 multiplexer and a 1:1 interpolator; and a phase converter connected to a last stage of the plurality of single-bit interpolator stages, configured to convert the two output signals into a single final output signal of a given phase. | ||
| 地址 | Armonk NY US | ||