Integrating channel SiGe into pFET structures

摘要

A structure including nFET and pFET devices is fabricated by depositing a germanium-containing layer on a crystalline silicon layer. The crystalline silicon layer is converted to silicon germanium in the pFET region to provide a thin silicon germanium channel for the pFET device fabricated thereon. Silicon trench isolation is provided subsequent to deposition of the germanium-containing layer. There is substantially no thickness variation in the silicon germanium layer across the pFET device width. Electrical degradation near the shallow trench isolation region bounding the pFET device is accordingly avoided. Shallow trench isolation may be provided prior to or after conversion of the silicon layer to silicon germanium in the pFET region. The germanium-containing layer is removed from the nFET region so that an nFET device can be formed on the crystalline silicon layer.

主权项

1. A method comprising:
obtaining a semiconductor on insulator substrate comprising a semiconductor layer that comprises crystalline silicon; epitaxially growing a layer comprising germanium on the semiconductor layer; removing a portion of the layer comprising germanium from the semiconductor layer to form a first region wherein the semiconductor layer is uncovered by the layer comprising germanium and a second region wherein the semiconductor layer is covered by the layer comprising germanium; forming a silicon germanium layer in the second region from the semiconductor layer and the epitaxially grown layer comprising germanium; forming a shallow trench isolation region on the substrate subsequent to epitaxially growing the layer comprising germanium; forming first source/drain regions on the semiconductor layer in the first region, and forming second source/drain regions on the silicon germanium layer in the second region and electrically isolated from the first region by the shallow trench isolation region.