Two-port SRAM cell structure

摘要

A memory cell is provided. The memory cell comprises a write port and a read port. The write port comprises a pair of cross-coupled inverters and a plurality of metal lines. The first inverter comprises a first pull-up device and a first pull-down device. The second inverter comprises a second pull-up device and a second pull-down device. The metal lines comprise a Vcc conductor line, a first Vss conductor line, and a second Vss conductor line. The first pull-down device has a source terminal coupled to the first Vss line. The second pull-down device has a source terminal coupled to the second Vss line. The read port comprises a cascaded device, a read word line, read bit line and a third Vss conductor line. The cascaded device comprises a read pull-down device and a read pass device. The read pull-down device has a source terminal coupled to the third Vss conductor line. The read pass device has a drain terminal coupled to the read bit line. The third Vss conductor line is coupled to a first power saving circuit. The Vcc conductor line is coupled to a second power saving circuit.

主权项

1. A semiconductor device comprising:
a plurality of SRAM memory arrays, each memory array comprising a plurality of memory cells, each memory cell comprising a write port and a read port, each write port comprising a first pull-down device and a second pull-down device, each read port comprising a read pull-down device; a source terminal of the first pull-down devices coupled to a first Vss conductor line; a source terminal of the second pull-down devices coupled to a second Vss conductor line; a source terminal of the read pull-down devices coupled to a third Vss conductor line; and wherein the third Vss conductor line is electrically isolated from both the first Vss conductor line and the second Vss conductor line.