System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlist

摘要

Systems and methods are disclosed for modifying the hierarchy of a System-on-Chip and other circuit designs to provide better routing and performance as well as more effective power distribution. A user specifies desired modifications to the design hierarchy and then the system automatically alters the hierarchy by performing group, ungroup, and move operations to efficiently and optimally implement the desired hierarchy modifications. Any modifications to port and signal names are automatically resolved by the system and the resultant RTL matches the function of the input RTL. The user then evaluates the revised hierarchy with regard to power distribution and routing congestion, and further hierarchy modifications are performed if necessary. A widget user interface facility is included to allow user-guided direction of hierarchy modifications in an iterative fashion.

主权项

1. A computerized method, implemented in a system of one or more processors, instruction memory and a database of RTL-level circuit description netlists, for restructuring a design hierarchy of an RTL-level circuit description netlist, comprising:
receiving by the one or more processors an initial RTL-level circuit description netlist; creating a hierarchy model for the initial RTL-level circuit description netlist; receiving from a user by the one or more processors one or more movement, group, or ungroup definitions whereby one or more circuit elements are directed to be moved, grouped, or ungrouped within the hierarchy model; planning and executing by one or more processors one or more of group, ungroup, and move operations in response to the one or more movement, group, or ungroup definitions, whereby one or more circuit elements are re-positioned in the hierarchy model, and whereby connectivity within a resultant revised circuit description netlist is automatically revised to maintain equivalent functionality to the initial RTL-level circuit description netlist; and saving into the database by one or more processors the resultant revised RTL-level circuit description netlist; wherein revision of the RTL-level circuit description netlist is performed prior to a physical placement of design elements during a layout process.