| 发明名称 | Operating method of memory having redundancy circuitry | ||
| 摘要 | In a method of operating a memory circuit, which includes a plurality of memory arrays each coupled with a corresponding input/output (IO) interface and a redundancy memory page a failing address of a failing bit cell is determined. The failing address is located in a memory page of one of the memory arrays. The method further includes repairing the failing bit cell by replacing the memory page with the redundancy memory page. | ||
| 申请公布号 | US8929137(B2) | 申请公布日期 | 2015.01.06 |
| 申请号 | US201414168257 | 申请日期 | 2014.01.30 |
| 申请人 | Taiwan Semiconductor Manufacturing Company, Ltd. | 发明人 | Yang Tien-Chun;Chih Yue-Der;Liu Shang-Hsuan |
| 分类号 | G11C11/34;G11C29/04;G11C16/04;G11C29/00 | 主分类号 | G11C11/34 |
| 代理机构 | Lowe Hauptman & Ham, LLP | 代理人 | Lowe Hauptman & Ham, LLP |
| 主权项 | 1. A method of operating a memory circuit, the memory circuit comprising: a plurality of memory arrays each coupled with a corresponding input/output (IO) interface;at least one information row, anda redundancy memory page; the method comprising: determining a failing address of a failing bit cell, wherein the failing address is located in a memory page of one of the memory arrays;registering bits of the failing address in the at least one information row, wherein the at least one information row includes a plurality of word lines; andrepairing the failing bit cell by replacing the memory page with the redundancy memory page. | ||
| 地址 | TW | ||