Tunable clock distribution system

摘要

A memory-like structure composed of variable resistor elements for use in tuning respective branches and leaves of a clock distribution structure, which may be used to compensate for chip-by-chip and/or combinatorial logic path-by-path delay variations, which may be due, for example, to physical variations in deep submicron devices and interconnections, is presented. A single system clocked scan flip-flop with the capability to perform delay test measurements is also presented. Methods for measuring combinatorial logic path delays to determine the maximum clock frequency and delays to program the variable resistors, as well as methods for calibrating and measuring the programmed variable resistors, are also presented.

主权项

1. A tunable clock distribution structure, comprising:
a clock input; a plurality of flip-flops with clock inputs; and a plurality of buffers, forming a structure configured to distribute clock signals from the clock input through at least one of the plurality of buffers to the clock inputs of the plurality of flip-flops, wherein each of the plurality of buffers comprises an inverter having an output coupled to a programmable variable resistor capable of assuming more than two different non-zero resistance values; wherein the programmable variable resistor comprises: a bit line; a word line; a programming transistor coupled to the word line and to the bit line; and a variable resistor coupled to the programming transistor and the inverter; wherein, in one mode, the programming transistor, the variable resistor and the inverter form a path for current to flow to program the variable resistor's resistance.